这门课程是关于在FPGA上实现不同的视频处理算法的。我们在高级综合[HLS]上实现该算法，用图像输入对其进行仿真，从HLS生成和导出IP。HLS IP与必要的视频处理管道[模块设计]集成在一起，并在FPGA器件上实现。
我们在HLS上有“实施Sobel边缘检测，膨胀，直方图均衡，快速角样算法”，然后是FPGA。为了在FPGA上调试算法，我们初始化了测试模式生成器[TPG] IP和视频DMA [VDMA]，以便在处理系统的参与下处理DDR上的图像流。
完成本课程后，您将能够：
利用HLS视频处理库，在HLS上实现并模拟不同的OpenCV算法
将HLS IP与视频处理管线与TPG和VDMA集成在一起，并在FPGA器件上实现。
在HLS上实现XfOpenCV [SDSoC]库以实现计算机视觉
将OpenCV算法迁移到XfOpenCV
This Course is on implementing different Video Processing algorithm on FPGA. We implement the algorithm on High Level Synthesis [HLS], simulate it with the image input, generate & export IP from the HLS. The HLS IP is integrated with the necessary video processing pipeline [block design] and implemented on the FPGA Device.
We have “Implemented Sobel Edge Detection, Dilation, Histogram Equalize, Fast Corner like algorithm” on HLS and then FPGA. For the debugging the algorithm on the FPGA, we have initialized the Test Pattern Generator [TPG] IP and Video DMA [VDMA] for processing the image streams on the DDR with the Processing System involvement.
After Completing this course you will be able to:
Utilized the HLS Video Processing Library and Implement as well as Simulate different OpenCV Algorithm on HLS
Integrating the HLS IP with Video Processing Pipeline with TPG and VDMA and Implementing on the FPGA Device.
Implementing the XfOpenCV [SDSoC] Library on HLS for Computer Vision
Migrating the OpenCV algorithm into XfOpenCV
MP4 | Video: h264, 1280×720 | Audio: AAC, 44100 Hz
Language: English | Size: 2.66 GB | Duration: 4h 21m
What you’ll learn
Implement different Computer Vision algorithm for Video Processing
Creating IP from the VIVADO High Level Synthesis
IP integration and configuration with Xilinx VIVADO
Xilinx SDK Application Development
Migrating the OpenCV algorithm on XfOpenCV
Simulating & Generating XfOpenCV codes in the VIVADO HLS
Integrating TPG, VDMA and Writing application for this blocks
Requirements
Basics of FPGA Design
High Level Synthesis Basics
PC with installed VIVADO, HLS and SDK [we will also show the steps for installation] Description
Who this course is for:
Electrical Engineering Enthusiast
Computer Science Enthusiast
FPGA Design Professional
Enthusiast of FPGA Design